1. Technical Field
Example embodiments relate to a wiring structure and a method of forming a wiring structure. More particularly, example embodiments relate to a wiring structure effective for reducing a parasitic capacitance and a method of forming the wiring structure.
2. Description of the Related Art
As semiconductor devices continue to become more highly integrated, the size of wirings, or interconnects, and the size of spacing between wirings in a semiconductor device continue to become more considerably decreased. It is preferred that the wirings in the semiconductor device have low resistance even though the wirings have greatly reduced widths; accordingly, the wirings are generally formed using metal having a low resistance, such as copper (Cu).
When low-resistance metal wirings are arranged at a small spacing, or interval, the parasitic capacitance between adjacent metal wirings can be considerably increased. To reduce the parasitic capacitance between metal wirings, an insulation layer between the wirings can be provided using a material having a low dielectric constant (i.e., low-k material). However, this approach is limited in its effectiveness with deeper device integration.